Hardware design of video transcoding based on RISC-V architecture
This paper introduces a VPU based on RISC-V architecture, detailing its hardware composition, technical characteristics and performance. Through rigorous testing, this article comprehensively evaluates its performance in video transcoding compression, video processing efficiency, and other aspects. The test results demonstrate that the RISC-V VPU excels in multiple performance metrics, showcasing significant technical advantages. It holds great application value in the field of video processing, providing an important reference for related technological research and applications.
Authors
- Chen Cheng (ORCID: https://orcid.org/0000-0001-9419-6945)
- Yuhang Zhu (ORCID: https://orcid.org/0000-0003-2026-8007)
- Zhi Quan Zhou (ORCID: https://orcid.org/0000-0003-1769-9367)
- Hong Liu (ORCID: https://orcid.org/0000-0003-3629-2626)
- Tianzheng Li
- Yang Zhou (ORCID: https://orcid.org/0009-0001-1157-5788)
- Kun Yang (ORCID: https://orcid.org/0009-0009-5172-9129)
Institutions
- China Telecom (China) (CN)
Publication Details
- Published
- 2025-07-24
- DOI
- https://doi.org/10.1117/12.3068408
- Primary Topic
- Image and Video Stabilization
- Type
- article
- Field-Weighted Citation Impact
- 0.00