Research on hardware acceleration technology based on SPARC microprocessor

Based on the SPARC instruction set architecture, this paper designs and implements vector and matrix instruction extensions, and designs a hardware acceleration unit through a high-level synthesis (HLS) method. A test platform is built to verify the correctness of each extended instruction function, and the improvement effect of each instruction on processor performance is compared. The results demonstrate significant performance gains in vector and matrix operations, highlighting the potential of the proposed approach for enhancing data parallel processing capabilities in SPARC-based systems.