A 25 fJ/Conv-step, 10-kHz, 119.8-dB SNDR incremental delta-sigma modulator using nested-current-mirror folded cascode OTA-based DT integrators for biomedical applications

A 3rd order feedforward single loop, 1-bit discrete time (DT) incremental delta-sigma modulator (IDSM) based on nested-current- mirror folded cascode (NFC) amplifier integrators is proposed in this paper. Moreover, the correlated double sampling (CDS) technique was used in the IDSM’s first integrator to reduce the offset and low frequency noise. The IDSM was designed in 180 nm CMOS process. Clocked at 5 MHz, it achieves 119.8 dB SNDR from circuit simulation over a 10 kHz bandwidth. It consumes 595.3 μW from a 1.8 V supply voltage, of which the first amplifier takes up 52.7%. The recorded Warden’s and Schreier’s figure of merits are 25 fJ/Conv-step and 192.6 dB respectively. The proposed modulator nested-current-mirror-amplifier-based integrators makes this ordinary modulator one of the most power saving DT DSMs.