A 40GS/s 8bit Time-Interleaved Time-Domain ADC Featuring SFDR-Enhanced Sample-and-Hold Circuit and Power-Efficient Adaptive Pulse Generator in 28nm CMOS

This paper reports a 40 GS/s 8b Time-Interleaved (TI) time-domain gated-ring-oscillator analog-to-digital converter (GRO-ADC). The smallest interleaving number of 32 is achieved with a single 8-bit GRO-ADC operating at $1.25 \mathrm{GS} / \mathrm{s}$ in 28 nm CMOS, leading to a low routing and front-end complexity between recently published works. An adaptive-working pulse generator eliminates the previous topology’s unnecessary pulse and minimizes the pulse generation power. The sampling front-end employs a linearity-enhanced boosted switch that supports short-time and high input voltage sampling, as well as a switched class-AB output buffer for low-power driving and nonlinear coupling suppression at high input frequency. Also, the multi-channel interleaved architecture also frees the GRO-ADC from single-channel calibration and reduces the sub-ADC design complexity. The TI GRO-ADC prototype is fabricated in a 28 nm CMOS process with an active area of $0.015 \mathrm{~mm}^{2}$. Under a maximum input swing of $0.8-\mathrm{V}_{\text {ppd }}$, it scores a measured peak SNDR of 40.3 dB and SFDR of 56 dB, respectively, at the conversion rate of $40 \mathrm{GS} / \mathrm{s}$, along with the Walden figures of merit (FoMw) of 41.6 fJ/conversion step.