An Ultra-Compact and Wideband D-band Power Amplifier in 28nm CMOS with Area-Efficient Coupled Line-Based Matching Network

This paper presents an ultra-compact and wideband D-band power amplifier (PA) utilizing area-efficient coupled line (CPL)-based matching networks. The design overcomes the size limitation in the signal propagation direction by employing CPL-based matching networks and shunt capacitors, enhancing bandwidth while achieving a compact form factor. Implemented in a CMOS 28 nm process, the proposed 3-stage PA achieves a $3-\mathrm{dB}$ bandwidth of 45.1 GHz with a peak gain of 12.2 dB, an $O P 1 \mathrm{~dB}$ of 7.6 dBm, and a power-added efficiency (PAEmax) of $\mathbf{1 0. 2 \%}$. With a core area of only $0.24 \times 0.065 \mathrm{~mm}^{2}$, the PA achieves the highest OP1dB per unit area among D-band PAs based on CMOS bulk process, making it a leading candidate for 2-D scalable D-band beamforming transmitter arrays.