A 116-132GHz -193.6dBc/Hz-FoM_T -252.8dB-FoM_J Frequency Synthesizer Using a 114fs-Jitter 60-GHz Double-Sampling PLL with Magnetic Parabolic Tuning and Injection-Locked Frequency Doubler

A wide-tuning-range (TR) low-phase-noise (PN) D-band frequency synthesizer cascades a mm-Wave double-sampling PLL (DSPLL) with a D-band differential-output injection-locked frequency doubler ($ILFM \times 2$). DSPLL consists of a dual-band VCO (DBVCO) with magnetic parabolic tuning and split primary coils, an injection-locked frequency divider (ILFD), and a superior double-sampling phase detector (DSPD) enabling a dual-path loop filter. $ILFM \times 2$ features differential outputs, self-oscillation current boosting, and center-tap injection. Fabricated in a 28-nm CMOS, the synthesizer measures TR of 12.9% from 116 to 132G, PN@1M normalized to 120G of -92.9~-106.1dBc/Hz, jitter ($1 \mathrm{k}-100 \mathrm{M}$) of 35.1-145.3fs, ${FoM}_{\mathrm{T}}$ @ 1 M of $-180.6 \sim-193.6 \mathrm{dBc} / \mathrm{Hz}$, and $\mathrm{FoM}_{\mathrm{J}}$ of -240.3~-252.8dB.