An 8-Lane 58 Gb/s/lane 0.66 pJ/bit Modulator Driver Electrical-IC for a 3-D Integrated Silicon Photonic Transmitter in 22 nm FD-SOI Process

A modulator driver circuit for electro-absorbtion modulators (EAMs) is designed in 22 nm FD-SOI technology as part of the electrical integrated circuit (EIC) of a 3D-integrated 8 -lane silicon photonic (SiPh) transmitter. The high driving voltage EAMs require, exceeding the breakdown voltage of the process is achieved by using stacked switches within the floating substrates of the SOI process. The high bitrate signal is delivered via level-shifters and pre-amplifiers to the high-voltage output stage. Limiting amplifiers and inductive peaking techniques are employed to increase the data rate (DR). Die level measurements show $1.87 \mathrm{~V}_{\mathrm{pp}}$ voltage swing with a 2 V supply at $58 \mathrm{~Gb} / \mathrm{s}$ where the transmission is still error-free ($\operatorname{BER}\lt 10^{-12}$). Optical measurements on the 3-D-hybrid integrated EIC with a photonic IC (PIC) show $50 \mathrm{~Gb} / \mathrm{s} /$ lane signal output. As a result of the implemented switching output stage, the overall EIC energy efficiency for the 8 lanes is as low as $0.66 \mathrm{pJ} /$ bit for $58 \mathrm{~Gb} / \mathrm{s}$ and $0.76 \mathrm{pJ} /$ bit for $50 \mathrm{~Gb} / \mathrm{s}$.