A 324-to-360-GHz –6-dBm Output Power THz Phase-Locked Loop in 40-nm CMOS

A 340-GHz THz phase-locked loop (PLL) composed of an 85-GHz integer-N charge-pump PLL (CPPLL) and a 340GHz frequency quadrupler (FQ) is proposed for THz communication applications. The FQ utilizes an optimal harmonic impedance matching technique to provide high conversion gain and output power. Given the targeted 340-GHz output frequency, this FQ enables the CPPLL to operate at a lower frequency of 85 GHz, significantly improving the THz PLL’s phase noise (PN) and frequency tuning range. Implemented in a 40-nm CMOS technology without ultra-thick metal layers, the proposed THz PLL can be locked from 324 to 360 GHz. It achieves an output power of −6 dBm, a reference spur of −35.5 dBc, a PN of $-87.4 \mathrm{dBc} / \mathrm{Hz}$ at the 1-MHz offset, and an RMS jitter of 145 fs integrating over 10 kHz to 100 MHz at 340 GHz. The THz PLL exhibits the highest figure of merit beyond 300 GHz.