A 127-to-156GHz 64QAM/256QAM Zero-IF CMOS Transceiver Chipset Achieving 42dB IRR and 17.8dBm Output Power
To address the demand for D-band applications requiring massive access with high modulation orders for users, a DC-coupled zero-IF(ZIF) transceiver chipset is proposed in this paper. To enhance the image rejection ratio (IRR), the transceiver adopts a wideband load-impedance robust stack coupler. To improve linearity, a biasing-free transconductance compensation mixer and an 8-way power combining power amplifier (PA) based on an enhanced magnetic coupling cavity with transmission line (EMCC-TL) are proposed. Measurement results show that the system achieves a maximum IRR of 47dB and an output power of 17.8dBm. Additionally, the transmitter(TX) and receiver(RX) achieve data rates of 6Gbps for 64QAM and 1.6Gbps for 256QAM with a 2GHz variable gain amplifier (VGA) operating bandwidth.
Authors
- Wei Zheng (ORCID: https://orcid.org/0000-0002-9864-938X)
- Baoyong Chi (ORCID: https://orcid.org/0000-0003-4399-4423)
- Fuyuan Zhao (ORCID: https://orcid.org/0000-0002-9463-2281)
- Wei Deng (ORCID: https://orcid.org/0000-0002-6323-4539)
- Haikun Jia (ORCID: https://orcid.org/0000-0003-4564-8938)
- Hongliang Wu
- Ziyuan Guo
- Xinyu Jiang (ORCID: https://orcid.org/0009-0007-8520-6751)
Institutions
- Tsinghua University (CN)
Publication Details
- Published
- 2025-06-15
- DOI
- https://doi.org/10.1109/rfic61188.2025.11082866
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China