A Low-Power High-Dynamic-Range Analog Correlator Based on Parametric Multiplication and Integration

This paper presents an analog correlator for radar and communication applications. The proposed correlator leverages a parametric mixer as the RF multiplier core, enabling a high dynamic-range while being low-power due to its fully passive architecture. Fabricated using 22-nm CMOS FDSOI technology, the prototype achieves a measured hardware dynamic range of 55 dB and supports a template symbol rate of 1 GSym/s with a scalable integration time. Additionally, the correlator unit can be extended into a multi-tap correlator network, delivering a computing efficiency of 300 TOPS/W. Comprehensive time- and frequency-domain characterization of the chip prototype demonstrates its effectiveness in applications such as time-of-arrival estimation and signal detection.