A Compact 25–32 GHz Frequency Doubler with up to 32% Efficiency and >39 dBc Harmonic Rejection in 22nm FDSOI

A frequency doubler with state-of-the-art power efficiency, high harmonic rejection, and a compact footprint is presented. The doubler utilizes a push-push architecture with a three-coil transformer load that creates a notch response, rejecting the $4^{\text {th }}$ harmonic. This enables pushing the doubler to higher output power, enhancing its efficiency. The doubler incorporates an input balun for fundamental suppression, thus exhibiting high rejection to all undesired harmonics. The design is implemented in 22 nm FDSOI with a core area of $0.054 \mathrm{~mm}^{2}$. The doubler achieves a measured output power of $\mathbf{4 - 6 ~ d B m}$ at an output frequency of $25-32 \mathrm{GHz}$ with an input power of 8 dBm. The measured $1^{\text {st }}$ and $4^{\text {th }}$ harmonic rejection ratios are greater than 42 and 39 dBc, respectively. The measured DC power is $11-15 \mathrm{~mW}$, yielding an efficiency of $17-32 \%$. To the authors’ knowledge, this is the highest reported efficiency for a frequency doubler implemented in a CMOS technology.