A Harmonic-Suppressing Gain-Boosted N-Path Receiver with Clock Bootstrapping for IoT Applications

This article presents a compact harmonic-suppressing gain-boosted N-path receiver for Internet of Things (IoT) applications. It features a passive harmonic rejection extension within the feedback path of an amplifier for early suppression of harmonic blockers and a pipeline down-mixer achieving over 3× passive gain. In addition, a low-power, scalable clock-boosting technique is introduced to enable operation under a low-voltage power supply. The prototype receiver (RX), implemented in 22-nm fully depleted silicon-on-insulator (FD-SOI) technology, occupies $0.048 \mathrm{~mm}^{2}$. Consuming only 1.27-5.48 mW, it operates across 0.25-3 GHz and achieves blocker 1-dB compression point (B1dB) of -3/-2 dBm at the $3^{\text {rd }} / 5^{\text {th }}$ harmonics, respectively. Furthermore, local oscillator (LO) leakage at the antenna port demonstrates superior performance compared to state-of-the-art designs, with worst-case -73 dBm across the entire frequency range.