JPEG XS hardware encoder based on modular pipeline design

JPEG XS is a relatively low computational complexity and visually lossless compression standard developed by the Joint Image Experts Group (JPEG). In this paper, a pipeline-based hardware implementation of JPEG XS encoder is proposed. Firstly, the coding process is decomposed into modules of pixel preprocessing, color space conversion, haar wavelet transform, dynamic quantization, rate control, and entropy coding, and modular design is adopted to reduce the critical path delay and the design of storage space reuse is adopted. In response to the heavy computational demands of wavelet transforms and entropy coding, a row-buffer-based dataflow mechanism was proposed to optimize memory bandwidth utilization. A configurable quantization table module is designed to support dynamic bit rate adjustment. The designed encoder can run up to 166Mhz with less hardware resource consumption and without external memory. Experimental results show that the architecture can achieve 2:1 to 8:1 compression ratios for 8K resolution (7680×4320) images. The decoded image has a peak signal-to-noise ratio (PSNR) of more than 45dB and structural similarity (SSIM) of more than 99% compared to the original image at a bit rate of more than 8.0 bpp with visually lossless effect, which is in line with the requirements of JPEG XS compression standard.