A 28-38 GHz Digitally-Assisted Frequency Tripler with Background Calibration in 55nm SiGe BiCMOS
This work presents a 28-to-38 GHz frequency tripler in 55-nm SiGe BiCMOS technology. An on-chip background calibration technique maximizes the output power, improving the fundamental harmonic rejection over wide input-frequency and input-power variations. The implemented tripler, which occupies an area of $0.4 \mathrm{~mm}^{2}$ and dissipates a power of 54 mW, achieves more than 40-dB fundamental harmonic rejection across a 3-dB bandwidth of 10.2 GHz (30.3%) and over 13 dB of input-power variation.
Authors
- Marco Rossoni (ORCID: https://orcid.org/0000-0003-2714-9043)
- Simone M. Dartizio (ORCID: https://orcid.org/0000-0001-5983-5609)
- Andrea Mazzanti (ORCID: https://orcid.org/0000-0002-0278-1942)
- Francesco Tesolin (ORCID: https://orcid.org/0000-0002-9743-5726)
- Andrea L. Lacaita (ORCID: https://orcid.org/0000-0003-0315-514X)
- Salvatore Levantino (ORCID: https://orcid.org/0000-0003-0895-1700)
- Riccardo Moleri
- D. Lodi Rizzini
- B. Nanino
- P. Granata
Institutions
- University of Pavia (IT)
- Politecnico di Milano (IT)
Publication Details
- Published
- 2025-06-15
- DOI
- https://doi.org/10.1109/rfic61188.2025.11082874
- Primary Topic
- Radio Frequency Integrated Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00