An 11.5mW 12.3-14.5 GHz Passive Mixer-First Receiver Front End Achieving 4.2dB NF and -5dBm B1dB

This work presents a low power, high dynamic range passive mixer-first receiver for the proposed 6G FR3 band. The proposed architecture achieves high performance at low power by directly driving the mixers with harmonically enhanced (HE) waveforms generated by a class $F^{-1}$ quadrature oscillator. Additionally, an overlap suppression front-end (FE) network is implemented that enables a wide range of mixer biases for optimal performance resulting in a more robust design to process and voltage variations. The $12.3-14.5 \mathrm{GHz}$ prototype is implemented in a FinFet process exhibiting a 4.2dB noise figure (NF), -5 dBm Blocker 1dB (B1dB) compression point, and 7.3 dBm out-of-band (OOB) third-order input intercept point (IIP3) with a total power consumption of 11.5 mW while occupying $0.28 \mathrm{~mm}^{2}$.

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Published
2025-06-15
DOI
https://doi.org/10.1109/rfic61188.2025.11082937
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
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article

An 11.5mW 12.3-14.5 GHz Passive Mixer-First Receiver Front End Achieving 4.2dB NF and -5dBm B1dB

Alyosha Christopher Molnar, Jamie C. Ye, Sanaz Sadeghi, A. Anton
Radio Frequency Integrated Circuit Design
article

An 11.5mW 12.3-14.5 GHz Passive Mixer-First Receiver Front End Achieving 4.2dB NF and -5dBm B1dB

Alyosha Christopher Molnar, Jamie C. Ye, Sanaz Sadeghi, A. Anton
article en

Abstract

This work presents a low power, high dynamic range passive mixer-first receiver for the proposed 6G FR3 band. The proposed architecture achieves high performance at low power by directly driving the mixers with harmonically enhanced (HE) waveforms generated by a class $F^{-1}$ quadrature oscillator. Additionally, an overlap suppression front-end (FE) network is implemented that enables a wide range of mixer biases for optimal performance resulting in a more robust design to process and voltage variations. The $12.3-14.5 \mathrm{GHz}$ prototype is implemented in a FinFet process exhibiting a 4.2dB noise figure (NF), -5 dBm Blocker 1dB (B1dB) compression point, and 7.3 dBm out-of-band (OOB) third-order input intercept point (IIP3) with a total power consumption of 11.5 mW while occupying $0.28 \mathrm{~mm}^{2}$.

Cornell University (US)
Affordable and clean energy
Openalex Percentile: Top 84%
Radio Frequency Integrated Circuit Design
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