A 28–40 GHz 6-Bit Variable Gain Phase Shifter with <0.4°/<0.31 dB PS RMS Phase/Gain Errors and 31.5-dB Gain Tuning Range

This paper presents a 28-40 GHz 6-bit variable gain phase shifter (VGPS) with 31.5-dB tuning range and low RMS phase/gain errors in 65-nm CMOS for millimeter-wave (mm-Wave) applications. A novel VGPS architecture based on switchless cascode variable gain amplifiers (VGAs) and a gain/quadrant-control IQ generator is proposed. To minimize device parasitics and input/output (I/O) impedance variations across different phase states, a switchless cascode VGA structure is employed to weight the I and Q signals, achieving low RMS phase/gain errors with 5 mW power consumption. In addition, cascode current-canceling (CCC) VGAs are integrated and co-designed with IQ generator, providing a 31.5-dB gain tuning range and wideband balanced IQ signals. Fabricated in 65-nm CMOS process, the proposed VGPS occupies a core chip area of 0.57 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Measurements show the VGPS achieves 6-bit phase control with -0.3 dB peak gain, <0.4° RMS phase error, and <0.31 dB RMS gain error across 28-40 GHz. It also provides 6-bit 31.5 dB gain control with <0.35 dB RMS gain error across 28-40 GHz. Furthermore, the measured average input 1-dB gain compression point (IP1dB) is >-1.1 dBm.

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Published
2025-06-15
DOI
https://doi.org/10.1109/rfic61188.2025.11082879
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
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article

A 28–40 GHz 6-Bit Variable Gain Phase Shifter with <0.4°/<0.31 dB PS RMS Phase/Gain Errors and 31.5-dB Gain Tuning Range

Ruixue Ding, Zhangming Zhu, Haohui Chen, Depeng Sun et al.
Radio Frequency Integrated Circuit Design
article

A 28–40 GHz 6-Bit Variable Gain Phase Shifter with <0.4°/<0.31 dB PS RMS Phase/Gain Errors and 31.5-dB Gain Tuning Range

Ruixue Ding, Zhangming Zhu, Haohui Chen, Depeng Sun, Tao Zhang, Shubin Liu, Lisheng Chen
article en

Abstract

This paper presents a 28-40 GHz 6-bit variable gain phase shifter (VGPS) with 31.5-dB tuning range and low RMS phase/gain errors in 65-nm CMOS for millimeter-wave (mm-Wave) applications. A novel VGPS architecture based on switchless cascode variable gain amplifiers (VGAs) and a gain/quadrant-control IQ generator is proposed. To minimize device parasitics and input/output (I/O) impedance variations across different phase states, a switchless cascode VGA structure is employed to weight the I and Q signals, achieving low RMS phase/gain errors with 5 mW power consumption. In addition, cascode current-canceling (CCC) VGAs are integrated and co-designed with IQ generator, providing a 31.5-dB gain tuning range and wideband balanced IQ signals. Fabricated in 65-nm CMOS process, the proposed VGPS occupies a core chip area of 0.57 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Measurements show the VGPS achieves 6-bit phase control with -0.3 dB peak gain, <0.4° RMS phase error, and <0.31 dB RMS gain error across 28-40 GHz. It also provides 6-bit 31.5 dB gain control with <0.35 dB RMS gain error across 28-40 GHz. Furthermore, the measured average input 1-dB gain compression point (IP1dB) is >-1.1 dBm.

Xidian University (CN)
Nature, Fundamental Research Funds for the Central Universities
Affordable and clean energy
Openalex Percentile: Top 84%
Radio Frequency Integrated Circuit Design
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A 28–40 GHz 6-Bit Variable Gain Phase Shifter with &lt;0.4°/&lt;0.31 dB PS RMS Phase/Gain Errors and 31.5-dB Gain Tuning Range — Ruixue Ding, Zhangming Zhu, et al. · (2025) | TGRS Research Map | TGRS