An 8-element 800MHz BW 0.083mm<sup>2</sup>/element Scalable Current-Mode True-Time-Delay Analog Combiner for Low SWaP-C Antenna Arrays

This paper presents a scalable current-mode true time delay (CMTTD) analog baseband combiner for large antenna arrays. The proposed combiner uses current-mode signal addition and alleviates the scalability-bandwidth trade-off in the state-of-the-art (SOTA) switched-capacitor-based combiners. An improved current-mode sample-and-hold (CSH) cell using a replica branch is proposed for wideband operation. A constant-slope-based phase interpolator (PI) generates programmable clock phases for signals from different antenna elements. The CMTTD IC is prototyped in 65 nm CMOS technology and supports 8 antenna elements with up to 800 MHz signal bandwidth. The combiner achieves a measured delay resolution of 4.59 ps, signal-to-noise-and-distortion (SINAD) ratio of 41.1 dB, and 37.3 dB at signal frequencies of 200 MHz and 800 MHz respectively, and EVM of -20.35 dB for 16QAM signal at $1.652 \mathrm{~Gb} / \mathrm{s}$ data rate. The IC occupies an active area of 0.083 $\mathrm{mm}^{2}$ per antenna element while consuming 7.5 mW DC power per antenna element from a 1 V supply.

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Published
2025-06-15
DOI
https://doi.org/10.1109/rfic61188.2025.11082954
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
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article

An 8-element 800MHz BW 0.083mm2/element Scalable Current-Mode True-Time-Delay Analog Combiner for Low SWaP-C Antenna Arrays

Sreeni Poolakkal, Ajinkya Kharalkar, Sumit Khalapure, Subhanshu Gupta et al.
Radio Frequency Integrated Circuit Design
article

An 8-element 800MHz BW 0.083mm2/element Scalable Current-Mode True-Time-Delay Analog Combiner for Low SWaP-C Antenna Arrays

Sreeni Poolakkal, Ajinkya Kharalkar, Sumit Khalapure, Subhanshu Gupta, Soumen Mohapatra, Shubham Jain, Rajesh Zele, Paavan Gouniyal
article en

Abstract

This paper presents a scalable current-mode true time delay (CMTTD) analog baseband combiner for large antenna arrays. The proposed combiner uses current-mode signal addition and alleviates the scalability-bandwidth trade-off in the state-of-the-art (SOTA) switched-capacitor-based combiners. An improved current-mode sample-and-hold (CSH) cell using a replica branch is proposed for wideband operation. A constant-slope-based phase interpolator (PI) generates programmable clock phases for signals from different antenna elements. The CMTTD IC is prototyped in 65 nm CMOS technology and supports 8 antenna elements with up to 800 MHz signal bandwidth. The combiner achieves a measured delay resolution of 4.59 ps, signal-to-noise-and-distortion (SINAD) ratio of 41.1 dB, and 37.3 dB at signal frequencies of 200 MHz and 800 MHz respectively, and EVM of -20.35 dB for 16QAM signal at $1.652 \mathrm{~Gb} / \mathrm{s}$ data rate. The IC occupies an active area of 0.083 $\mathrm{mm}^{2}$ per antenna element while consuming 7.5 mW DC power per antenna element from a 1 V supply.

Indian Institute of Technology Bombay (IN), Washington State University (US)
Affordable and clean energy
Openalex Percentile: Top 84%
Radio Frequency Integrated Circuit Design
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An 8-element 800MHz BW 0.083mm<sup>2</sup>/element Scalable Current-Mode True-Time-Delay Analog Combiner for Low SWaP-C Antenna Arrays — Sreeni Poolakkal, Ajinkya Kharalkar, et al. · (2025) | TGRS Research Map | TGRS