A 12-Bit 6-GS/s Time-Interleaved SAR ADC with On-Chip Mismatch Calibration in 28nm CMOS Technology

This article presents a wideband 12 bit 6 GS/s time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a 28 nm CMOS technology addressing FMCW based radar, as well as instrumentation applications demanding excellent ADC linearity. The proposed ADC makes use of a wideband front-end featuring two subsequent ranks of pseudo-differential push-pull input buffers to distribute the input signal to 1912 bit $375 \mathrm{MS} / \mathrm{s}$ SAR-ADC lanes. Each SAR-ADC lane takes advantage of a sub-2 radix split CDAC with a 9% overrange, a distributed sample switch implemented as an isolating T-switch and a fully loop-unrolled comparator architecture. Furthermore, the ADC system features an on-chip digital calibration engine to correct inter-channel mismatch effects such as gain, offset and sample-phase mismatch. Measurement results reveal an SNDR and SFDR of 50 dB and 62.8 dBc respectively for a $1 \mathrm{~V}_{\text {ppd }}$ single tone sine wave input signal across the entire 3 GHz Nyquist-band with an HD3 of 72.7 dBc at Nyquist. The complete ADC system draws 2.5 W from four power supplies ($1 \mathrm{~V}, 1.8 \mathrm{~V}, 2.5 \mathrm{~V}$ and -1.3 V), resulting in a Schreier Figure-of-Merit ($\mathrm{FoM}_{\mathrm{s}}$) of $\mathbf{1 4 5} / \mathbf{1 4 1} \mathrm{dB}$ for low and high-frequency inputs respectively.