Design of Terahertz Level Frequency Doubling Circuit and Characteristic Optimization

Caused by inappropriate allocation of the mismatches during broadband matching, the boosted dynamic dc current of the frequency doubler (FD) would deteriorate the broadband efficiency. The analysis and design of a frequency doubler based on 40-nm CMOS technology is presented in this short. In order to tackle the critical challenges related to bandwidth efficiency and the footprint of CMOS push-push frequency doublers, several strategies can be explored. These strategies aim to improve the overall performance by optimizing the design parameters and incorporating advanced techniques to minimize the area and enhance the power efficiency. To get the greatest performance, the transistor size and output impedance matching are carefully optimized. With a bias voltage of 1.1 V, the doubler's observed peak power is +4.1 dBm at 362 GHz and > 3 dBm at 300-426 GHz. These were accomplished at 183 GHz with an input power of 8-9 dBm, yielding a 41-45 dB power conversion gain. As far as we are aware, these are the favorable outcomes attained for a terahertz doubler in CMOS.