Design and Implementation of Digital Array Radar Signal Generation, Acquisition, and Processing Based on RFSoC

In recent years, research achievements in Digital Array Radar (DAR) have become increasingly prominent. However, traditional radar signal acquisition and processing frameworks relying on combinations of Radio Frequency (RF) front-end circuits and Field-Programmable Gate Array (FPGA) signal processing boards still exhibit inherent limitations, making it difficult to meet modern radar systems’ comprehensive requirements for miniaturization, high flexibility, real-time operation, and multi-channel cooperative processing. To address these challenges, this paper proposes a full-process architecture for DAR signal generation, acquisition, and processing based on Radio Frequency System-on-Chip (RFSoC) technology. For radar signal generation and acquisition, RFSoC’s built-in RF data converter and a Finite State Machine (FSM) design are utilized to construct an integrated architecture enabling synchronized signal generation and acquisition. In signal processing, leveraging the heterogeneous computing characteristics of the Programmable Logic (PL) and Processing System (PS), a task division strategy is implemented to establish a cascaded processing pipeline. This pipeline sequentially performs pulse compression, Moving Target Detection (MTD), Digital Beamforming (DBF), Constant False Alarm Rate (CFAR) detection, target integration, and sum-and-difference amplitude comparison monopulse angle measurement. Experimental results demonstrate the proposed architecture’s capability to achieve stable tracking of dynamic targets in complex field environments. The solution provides a practical technical pathway for engineering next-generation software-defined and miniaturized digital array radar systems.