Low Temperature Synergistic Optimization of Electrical and Stability Performance of a-ZnO TFTs

Achieving both high electrical performance and high stability in amorphous zinc oxide thin-film transistors (a-ZnO TFTs) is difficult, which undoubtedly greatly limits their practical application in the field of advanced flexible electronics. This study proposes a strategy to simultaneously improve the electrical performance and stability of a-ZnO TFTs by utilizing copper (Cu) as the source-drain electrode and optimizing key fabrication parameters, including carrier gas flow rate, sputtering time, and low-temperature annealing. The experimental results show that when the carrier gas flow rate is 10 SCCM, sputtering time is 10 minutes, and annealing temperature is $250^{\circ} \mathrm{C}$, a-ZnO TFTs exhibit optimal electrical and stability performance. Specifically, the $\mu_{\mathrm{FE}}$ reaches $13.1 \mathrm{~cm}^{2} \cdot \mathrm{~V}^{-1} \mathrm{~s}^{-1}$, the $\mathrm{I}_{\text {on }} / \mathrm{I}_{\text {off }}$ is $6.9 \times 10^{6}$, the $\mathrm{V}_{\text {th }}$ is -0.8 V, and the SS is $1.9 \mathrm{~V} \cdot \mathrm{dec}^{-1}$. Notably, the threshold voltage drift ($\Delta \mathbf{V}_{\text {th }}$) under positive bias stress (PBS) and negative bias stress (NBS) is 3.6 V and -1.0 V, respectively. The device design and fabrication method developed in this study provide a simple yet effective approach to enhancing both the electrical performance and stability of a-ZnO TFTs, offering a valuable reference for further research and development in the field of electronics.