Optimizing True Random Number Generation on Fpgas: Leveraging Dynamic Clock Phase Shifts and Fast Carry Chains for Enhanced Performance and Efficiency in 32-Bit and 64-Bit Implementations

TRNGs(True Random Number Generators) are essential components in numerous security applications, providing essential randomness for cryptographic operations and other sensitive tasks. While analog-driven sources of randomness are frequently utilized, there is an increasing need for digital solutions, particularly for implementation on FPGA based systems. This study presents a novel technique designed to streamline TRNG design on FPGA devices. The proposed method capitalizes on the runtime capabilities of Digital Clock Managers (DCMs) to manipulate the phase shift between two clock signals. By dynamically adjusting the phase difference, this approach induces one or more flip-flop sin to the metastability zone, exploiting it as a source of unpredictability within the system. Moreover, the investigation explores the use of the fast carry-chain hardware primitive to augment the randomness of generated bits. Moreover, a robust on-chip post-processing strategy is outlined to sustain TRNG throughput while preserving randomness. This approach ensures that the random number generation meet stringent security requirements while maximizing system efficiency. The research encompasses implementations in both 32 and 64 data widths using Verilog HDL and synthesis on Xilinx Zynq FPGAs. Evaluation metrics such as area, latency, and power consumption are thoroughly assessed to gauge the effectiveness and efficiency of the proposed designs.