Transistor-Level A2 Trojan Anomaly Detection Method
As the complexity of integrated circuit (IC) design continues to increase and manufacturing becomes more globalized, IC engineers are increasingly relying on third-party intellectual property (IP) cores to reduce costs and accelerate development. However, this trend has also introduced significant security risks, particularly the threat of hardware Trojans. While numerous hardware Trojan detection methods have been developed, most are focused on the digital domain, with relatively little research dedicated to the analog domain. To bridge this gap, this paper presents a novel detection method for A2 Trojans in the analog domain, specifically targeting transistor-level detection. Our approach employs the Isolation Forest algorithm to analyze the transistor-level netlist of the IP core and detect anomalous transistors. These detected anomalies are then expanded into a graph structure based on the relationships between transistors, followed by the application of the VF2 graph matching algorithm to identify potential A2 Trojan structures. This method effectively overcomes the limitations of existing detection techniques in the analog domain, enhancing both the comprehensiveness and accuracy of hardware Trojan detection.
Authors
- Jialong Song (ORCID: https://orcid.org/0009-0002-4939-9430)
- Jiubin Tan (ORCID: https://orcid.org/0000-0002-0941-7932)
- Yang Zhang
- Jianming Zhang (ORCID: https://orcid.org/0000-0002-4278-0805)
- Jiayu He (ORCID: https://orcid.org/0009-0007-6419-0690)
- Xing Hu
Institutions
- National University of Defense Technology (CN)
- Xiamen Institute of Building Research Group (CN)
- Changsha University of Science and Technology (CN)
Publication Details
- Published
- 2025-05-23
- DOI
- https://doi.org/10.1109/eeiss65394.2025.11086025
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.00