A Spike Sorting SoC With Δ-Based Spike Detection and End-to-End Implementation of Autoencoder Feature Extraction Using Analog CIM

To process the substantial data generated from on-chip neural recordings, a robust spike sorting (SS) system-on-chip (SoC) with minimal latency is essential to ensure timely response in closed-loop brain–computer interface (BCI) applications. In this article, we report a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $</tex-math> </inline-formula>-based SS SoC featuring the first on-chip incorporation of analog computing-in-memory (CIM) end-to-end binary autoencoder neural network (B-AENN) feature extraction to lower computation energy while maintaining high accuracy. The use of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $</tex-math> </inline-formula>-spike-signals in this work not only improves the noise resilience of the SS system but also provides a better foundation for feature extraction, leading to enhanced accuracy. The integration of B-AENN enables a more adaptive approach, in comparison to predefined methods, to extract features, especially for closely resembling spikes. Furthermore, by relocating the spike detection and feature extraction processes to the analog domain, our proposed system overcomes the analog-to-digital converter (ADC) conversion bottlenecks in increasingly dense channels. Fabricated using a 65-nm CMOS technology process, the prototype chip facilitates exceptional performance with 5.1-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>s computational latency, making it ideal for closed-loop, real-time applications and achieving a classification accuracy of 94.54% while consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.11~{\mu }$</tex-math> </inline-formula>W/ch, representing the highest reported on-chip classification accuracy to date.

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Publication Details

Journal
IEEE Journal of Solid-State Circuits
Published
2025-07-24
DOI
https://doi.org/10.1109/jssc.2025.3589523
Primary Topic
Industrial Vision Systems and Defect Detection
Type
article
Field-Weighted Citation Impact
0.00

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article

A Spike Sorting SoC With Δ-Based Spike Detection and End-to-End Implementation of Autoencoder Feature Extraction Using Analog CIM

Minkyu Je, Sohmyung Ha, Ik‐Joon Chang, Edward Choi et al.
IEEE Journal of Solid-State Circuits
Industrial Vision Systems and Defect Detection
article

A Spike Sorting SoC With Δ-Based Spike Detection and End-to-End Implementation of Autoencoder Feature Extraction Using Analog CIM

Minkyu Je, Sohmyung Ha, Ik‐Joon Chang, Edward Choi, Vincent Lukito
article en

Abstract

To process the substantial data generated from on-chip neural recordings, a robust spike sorting (SS) system-on-chip (SoC) with minimal latency is essential to ensure timely response in closed-loop brain–computer interface (BCI) applications. In this article, we report a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $</tex-math> </inline-formula>-based SS SoC featuring the first on-chip incorporation of analog computing-in-memory (CIM) end-to-end binary autoencoder neural network (B-AENN) feature extraction to lower computation energy while maintaining high accuracy. The use of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $</tex-math> </inline-formula>-spike-signals in this work not only improves the noise resilience of the SS system but also provides a better foundation for feature extraction, leading to enhanced accuracy. The integration of B-AENN enables a more adaptive approach, in comparison to predefined methods, to extract features, especially for closely resembling spikes. Furthermore, by relocating the spike detection and feature extraction processes to the analog domain, our proposed system overcomes the analog-to-digital converter (ADC) conversion bottlenecks in increasingly dense channels. Fabricated using a 65-nm CMOS technology process, the prototype chip facilitates exceptional performance with 5.1-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>s computational latency, making it ideal for closed-loop, real-time applications and achieving a classification accuracy of 94.54% while consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.11~{\mu }$</tex-math> </inline-formula>W/ch, representing the highest reported on-chip classification accuracy to date.

IEEE Journal of Solid-State CircuitsVol. 61(4)
New York University Abu Dhabi (AE), Korea Advanced Institute of Science and Technology (KR), Kyung Hee University (KR)
Institute for Information and Communications Technology Promotion
Openalex Percentile: Top 75%
Industrial Vision Systems and Defect Detection
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