HIDC: Heterogeneous-ISA Dynamic Core

Heterogeneous-ISA architectures are emerging as an alternative for better performance and energy efficiency. These systems exploit ISA affinity within and across programs by executing them dynamically on the most suited ISA core. However, heterogeneous-ISA chip multiprocessor incurs significant power and area overheads compared to single-ISA systems. Also, due to switching overhead between different ISA cores, the migration opportunities are constrained to coarse-grained program phases (order of 100M instructions), limiting the potential of harnessing ISA diversity. We propose Heterogeneous-ISA Dynamic Core (HIDC), an architecture which reduces the migration overhead by supporting different ISAs within a single core and an improved migration strategy called Simultaneous Transformation. HIDC improves single-threaded performance and energy efficiency by exploiting ISA diversity at a finer granularity and reducing power consumption compared to heterogeneous-ISA CMP. To optimally schedule program phases as per their ISA affinity, we present a low-overhead perceptron-based scheduling mechanism along with its implementation in hardware. Overall, HIDC improves by 52.89% and 33.93% in performance per joule metric over heterogeneous-ISA CMP and single x86 ISA core, respectively. It achieves 4.62% and 19.06% performance improvement relative to heterogeneous-ISA CMP and single x86 ISA core. Also, it leads to ∼20× reduction in cross-ISA migration latency.