PSqueue: an Enhanced Memory Scheduling Queue Architecture For Multi-Threaded Streaming Memory Access

The surge in core counts of modern processors has led to a notable reduction in available memory bandwidth per core. This paper introduces PSqueue, an enhanced memory scheduling queue architecture designed to optimize multithreaded streaming memory access on Loongson processors. The proposed architecture addresses two significant challenges identified in pre-silicon performance evaluations: the stalling of compression-based memory scheduling queue during rank-level refreshes and Network-on-Chip(NoC) congestion during highly intensive memory accesses. To mitigate these issues, PSqueue, the combination of a preprocessing queue and a selection-based memory scheduling queue, is introduced. The selection-based scheduling queue allows ready-to-issue requests to bypass blocked ones, enhancing out-of-order scheduling capabilities. The preprocessing queue alleviates congestion by providing an escape channel for memory requests, thereby increasing the overall throughput of the memory controller. Experimental results indicate that the PSqueue architecture achieves an average memory bandwidth gain of 4.04%, with peak gains of 6.48% in multi-threaded streaming memory access scenarios. These innovations are in preparation for the design of the next-generation Loongson processors.