An optimised AES algorithm and its FPGA implementation for secure information

Security algorithms play a crucial role across various communication networks, encompassing both wired and wireless infrastructures. As technology rapidly evolves, particularly in the realm of 5G communications, the demand for more robust security measures is becoming increasingly prominent. Research to date has focused on the AES 128-bit encryption standard, with its implementation being extensively tested, synthesised, and applied to different FPGA platforms such as Spartan, Virtex, and Kintex. Nevertheless, existing studies fall short in providing an AES algorithm optimised for minimising power consumption, reducing latency, and conserving space, all of which are critical for effective security. This study introduces an enhanced AES algorithm tailored for FPGA implementation, specifically designed to meet the stringent criteria of reduced latency, decreased power usage, and lower spatial requirements for the purposes of simulation and synthesis, using Xilinx-ISE v14.7 tool.