Design of low power low area SRAM cell at 180 nm, 90 nm and 45 nm technology nodes

In this paper, a new SRAM topology cell is proposed with low power and low area in different technology nodes: 180 nm, 90 nm and 45 nm. The power consumption results of the new SRAM topology is compared with the conventional 6T SRAM cell and SRAM cell implemented with LECTOR technique. The schematic design of these SRAM cells are implanted in the S-Edit, for generating spice code of the circuit T-Spice is used and the wave forms are observed in the W-Edit of the tanner tool software. The proposed SRAM cell at 45 nm technology node has got better power consumption compared to the remaining SRAM topologies.