Design and Simulation of a Carry Save Adder (CSA) using NAND Gate in CMOS 180nm Technology
Using CMOS 180nm technology, this study explores the design and simulation of digital circuits which include basic logic gates to Carry Save Adder (CSA). With a focus on optimizing power consumption and propagation delay, the designs are implemented in LTspice.
Authors
- Sreenidhi Prabha Rajeev (ORCID: https://orcid.org/0000-0001-5756-477X)
- Gautham Jayesh
Institutions
- Amrita Vishwa Vidyapeetham (IN)
Publication Details
- Published
- 2025-04-24
- DOI
- https://doi.org/10.1109/amathe65477.2025.11080777
- Citations
- 1
- Primary Topic
- Radiation Effects in Electronics
- Type
- article
- Field-Weighted Citation Impact
- 0.73