Design and Implementation of 10 Bit SAR ADC for High speed applications

Analog-to-digital converters (ADCs) are the key components in interfacing the real-world with the digital domain. Low power and high-resolution Successive approximate Register (SAR) type ADCs are very much required in the AI-IoT portable applications. In portable applications, the restrictions on the available power and the importance of the quality of digital data are taken as the challenges. To make the SAR-ADC power efficient, all the blocks of it should be designed with low power techniques. Our design contains mostly analog blocks, like, Op-Amp, Comparator, current mirrors, biasing scheme and switching scheme and few digital blocks like D-ff (D-flip flop). In this work, A $3.3 \mathrm{~V}-0.18 \mu \mathrm{~m}$ CMOS process 10-bit and 10 MSPS power-efficient SAR-ADC is presented to achieve ENOB of <9-bits, power of 5 mV.