Evaluation of Programmable Packet Processing Framework Using P4 and XDP Enabled Switches

The increasing demand for low-latency, highthroughput packet processing has driven the exploration of programmable dataplane technologies such as P4 and eBPF/XDP. This paper evaluates the suitability of integrating P4 and XDP, which combines the flexible programmability of P4 running on a programmable data plane switch's pipeline and the expedited processing capabilities of Generic XDP running on the kernel of the hardware switch's CPU. The framework is implemented on the Tofino-1 switch for three different applications: forwarding, filtering and monitoring. The results show that P4+XDP performs similar to P4 in the simple forwarding application, but improves performance in filtering application, such as handling anomaly packets separately. This is attributed to XDP's kernel-bypass capabilities and proximity to the deparser in the Tofino-1 switch, enabling low-latency packet filtering. The studies also show that P4+XDP enhances packet processing by achieving an average latency reduction of 35 %, with values as low as 40 nanoseconds. It provides over 98% packet delivery due to its enhanced processing capability.