A 7-Bit Vector-Sum Phase Shifter for LEO Satellite Communication in 90-Nm CMOS Process

This paper presents a 7-bit vector-sum phase shifter for low-earth-orbit satellite communication. The phase shifter consists of a differential-type quadrature all-pass filter (QAF) and an analog differential vector adder, where a matching network is inserted between the QAF and vector adder to minimize insertion loss further. Theoretical analyses are performed to account for the loading effect on the QAF while providing design methodology to minimize phase and amplitude errors. Two 8-bit current digital-to-analog converters (IDACs) are used to supply the bias current and determine the weighting of the I/Q signals for the vector adder, enabling full-range phase shifting with steps smaller than 3°. Fabricated in the TSMC 90-nm CMOS process, the digital phase shifter occupies a chip area of 0.63 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Over the frequency band of 27 GHz to 31 GHz, the phase shifter achieves an average gain between 0.13 dB to 1.36 dB, an RMS gain error between 0.68 dB to 0.9 dB, and a high phase shift accuracy with an RMS phase error between 0.18° to 0.21°. Compared with other vector-sum phase shifters, this work achieves the highest figure-of-merit while consuming the lowest power of 10 mW.