ReRAM/CMOS Array Integration and Characterization via Design of Experiments

Abstract No two fabricated Resistive Random Access Memory (ReRAM) devices are alike. Each device can have its own individual optimal set of operating parameters that gives the best performance. However, in an array each device needs to be measured in similar operating settings. Therefore, it is necessary to find the optimal settings where most devices will have the best performance across the entire array population. Traditional sampling methods require a large number of tests within an experimental space, which is time‐intensive and resource‐draining. As an alternative, this study proposes the adoption of the Latin square method under the Design of Experiments (DoE) framework for the characterization and performance optimization of arrays of ReRAM devices. This innovative approach drastically reduces the number of experimental tests, thereby offering a faster way to discern the impact of each factor and fine‐tune device parameters effectively. The core objective of employing this DoE technique is to harness its potential for optimizing parameters that significantly enhance the ON/OFF ratio and endurance of ReRAM devices. The optimization technique, performed on a CMOS‐integrated 20 k array of ReRAM devices, increases the device yield by ≈84%, compared to the previous integration with an unoptimized technique.