Permanent-Magnet Biased Inductor for DC Fault-Current Limiting Applications

This paper presents a study on a Permanent-Magnet Biased Inductor (PMBI) topology designed for Fault Current Limiting (FCL) applications. It explores the design, implementation, and validation of a Saturation Gap PMBI topology, which enhances system protection by delaying the rise of fault current, thereby allowing sufficient time for circuit breakers to operate effectively. Both series and parallel PMBI configurations are analyzed, evaluating their performance through simulation studies. A setup utilizing UU-type asymmetrical cores with integrated permanent magnets (PM) was developed. Later, this topology was used for DC FCL. Finite Element Analysis (FEA) simulations using FEMM 4.2, along with experimental validation, confirm that the inductance of PMBI initially increases with rising current but decreases beyond a critical threshold due to core saturation. In addition, the hardware integration and verification of PMBI was implemented in a DC FCL application. The results obtained indicate that conventional inductors allow fault currents to rise rapidly, potentially overloading protective mechanisms. In contrast, PMBI-based FCL effectively restricts the rise in fault current by delaying the response time by 200%, which can be used to offer enhanced protection for DC grids, renewable energy systems and industrial power networks.