Comprehensive Analysis of a 1.2 kV 4H-SiC DMOSFET with an Improved Short Circuit Withstand Time

In a recent work, we proposed a novel method to design the drift layer of $\mathbf{4 H}$-SiC $\mathbf{D}$-MOSFETs to maximize the short circuit withstand time, $t_{S C}$, at the cost of $\lt 5 \%$ increase in specific on resistance, $R_{ {onsp }}$. In this work, devices designed using the proposed method is compared against that designed using the conventional method in terms of their avalanche ruggedness through unclamped inductive switching (UIS) test and their static performance after incorporating self heating effect. It is found that the proposed device has better avalanche ruggedness as compared to the reference device. For inductance, $L=100 \mu \mathrm{H}$, the proposed device has $\mathbf{9. 6 \%}$ decrease in peak discharge current, $I_{a v}$ and a $\mathbf{1 2. 5 \%}$ increase in effective drain-to-source breakdown voltage at peak discharge current, $V_{B R, { eff }}$. On the other hand, $R_{ {onsp }}$ of the proposed device degrades more rapidly than conventional device due to the positive thermal coefficient of drift resistance and the increased contribution of the drift resistance to the overall $R_{{onsp }}$ in the former device.