High-Performance and Resource-Efficient Squaring Architecture for FPGA Platforms

Hardware-intensive signal processing has seen tremendous growth over the last few decades, owing to the advances in VLSI technology. This has resulted in a significant paradigm shift, wherein different computational functionalities are increasingly implemented using different hardware platforms. The squaring function is one such operation that finds its application in many signal-processing tasks. Since squaring is a specific case of multiplication, traditional multiplication algorithms can be adapted to create high-performance squaring architectures. In this paper, we present a squaring architecture that is based on the CORDIC algorithm. The hardware efficiency of the CORDIC algorithm enables it to compute different mathematical functions using only shift and add operations. By operating the algorithm in linear mode, the CORDIC computations can be modeled to emulate the squaring function. Our 8-bit CORDIC-based squaring architecture shows a 25% and 38% reduction in PDAP over the existing best design for ASIC and FPGA platforms, respectively.