Design of an SPI interface based on ferroelectric memory

This paper presents a high-speed SPI interface design for ferroelectric memory (FRAM), optimized for embedded systems and IoT applications. The design integrates serial-to-parallel and parallel-to-serial conversion circuits, along with an opcode enable module, achieving a transmission rate of 25 Mbit/s. Functional simulations demonstrate reliable FRAM read/write operations and status register control. The modular architecture ensures high compatibility and scalability, making it suitable for various embedded storage applications. This work provides a robust solution for high-speed non-volatile memory and lays the foundation for future larger-capacity FRAM applications.