Research on production date recognition based on depthwise separable convolution and FPGA platform

Production date recognition is a key issue in the medical and food industries, where the consequences of consuming expired products would be hazardous to the health of consumers. Existing work focuses on the improvement of algorithmic accuracy, which is increasingly escalating in power consumption and cost to the detriment of industrial production. To reduce the cost and power consumption, edge computing for production date recognition algorithms becomes a major challenge. To address these challenges, this paper investigates the hardware/software co-design approach to build a lightweight neural network, builds a hardware accelerator on FPGA with systolic array architecture. The experimental results show that the number of parameters of the lightweight character classification network proposed in this paper is compressed to 9.4K, and the recognition rate in the self-built dataset reaches 96.9%, with the total power consumption of the system only 3.084W.