Hardware acceleration design for infrared small target detection based on joint local contrast using FPGA

As infrared small target detection technology continues to develop, the computational load and complexity of algorithms increase, making deployment on general-purpose processors insufficient to meet real-time requirements. To enhance the processing speed of detection algorithms, this study designs a dedicated hardware acceleration scheme for the joint local contrast detection algorithm based on a high-concurrency Field-Programmable Gate Array (FPGA) hardware platform. By implementing algorithm precision optimization, scale adjustment, and time-division multiplexing techniques, the real-time performance of the algorithm is significantly improved. Experimental results show that the system has a static power consumption of 5.73W, and with a clock frequency of 100MHz, the processing time for a 256×256 image is 2.25ms, achieving a real-time frame rate of 444FPS. Compared to the single-frame processing time of 9.70s on a PC, the acceleration factor reaches 4311:1.