Impact of Scaling and Interface Roughness on Drain Current in Nanosheet and Nanowire FETs: A 3D Monte Carlo Analysis

A 3D finite-element Monte Carlo simulation toolbox, incorporating Schrödinger equation-based quantum corrections, is employed to analyze the performance of nanosheet (NS) and nanowire (NW) field-effect transistors (FETs), which emerged as promising candidates for sub-3 nm CMOS technology. The study investigates the impact of scaling gate length and oxide thickness, increase in source/drain doping concentration, and interface roughness on these architectures. Results indicate that NS-FETs achieve higher ON currents than NW FETs. However, scaling the gate length below 12 nm reduces the drain current in both devices with a ⟨110⟩ channel orientation – by 9.4% in NS and 7.7% in NW. To understand this decline, valley population and average electron velocity are examined. Scaling dielectric thickness has a smaller effect on NW-FETs with 12 nm and 10 nm gate lengths compared to NS-FETs. In contrast, changes in maximum doping concentration have a greater impact on NW than NS, due to better electrostatic control and increased carrier injection resulting from reduced source/drain resistance. A back-scattering effect is observed in the 12 nm and 10 nm gate length devices, particularly NWs, but it can be mitigated by increasing doping concentration. Interface roughness significantly degrades drain current (IDD), with a more pronounced impact on NWs. Their smaller surface-to-volume ratio and stronger quantum confinement increase sensitivity to roughness variations, as most carriers are closer to the surface, leading to more scattering events. On the contrary, NSs, despite interface roughness, benefit from a larger conductive cross-section, maintaining higher effective mobility in the device channel.