Performance and Reliability of a Double-Gate FinFET

This study aims to presents a comprehensive analysis of a fast-emerging field effect transistor (FET) namely, the double gate (DG)-FinFET as the basic block of any multi-gate FinFET structure with an objective of highlighting the key benefits of a DG-FinFET over various parameters such as its device characteristics, performance metric, leakage current reduction, scalability and industrial acceptance over other beyond CMOS devices. The significant amount of work carried out by researchers and academic scholars has been blended to present a relevant comparison of DG-FinFET over other devices such as Shorted Gate Fully Depleted Silicon on Insulator (SG-FDSOI) MOSFET. Additionally, the effect of incorporating high-ê dielectric materials has also been reviewed to highlight performance enhancements in DG-FinFET. The performance parameters which have been reviewed are subthreshold slope, leakage current, drain induced barrier lowering (DIBL), transconductance, and threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>) over its speed, and short-channel-effects (SCEs) reduction. It is strongly believed that this paper will provide significant help to researchers exploring the possibilities offered by DG-FinFETs, particularly in advancing sustainable electronics and aligning with SDG-9, which emphasizes innovation and sustainable industrial practices.