Model–Architecture Codesign for High-Performance and Energy-Efficient SAR ATR on FPGA

Synthetic Aperture Radar (SAR) Automatic Target Recognition (ATR) is a crucial technology in remote sensing. SAR devices, such as those on satellites like Sentinel-1A, collect SAR data for various applications. However, state-of-the-art CNN-based approaches for SAR ATR have high computational complexity. This makes them unsuitable for deployment on resource-limited platforms. In this paper, we present a novel model-architecture co-design for SAR ATR on Field Programmable Gate Arrays (FPGAs). Our proposed co-design consists of: (1) A novel multi-layer Graph Neural Network (GNN) model for SAR ATR with low computational complexity and a small number of parameters. (2) An optimized hardware architecture on FPGAs, ensuring low-latency, high-throughput, and energy-efficient execution of the GNN model. For model design, we leverage attention mechanisms to enhance classification accuracy. We then use knowledge distillation to train a simplified GNN model. This reduces computational cost while maintaining nearly the same accuracy. Additionally, we apply model pruning to further reduce computational complexity without compromising performance. To maximize computational parallelism, we introduce a customized hardware accelerator on FPGA. This accelerator uses the Scatter-Gather paradigm to efficiently manage the irregular computation and memory access patterns inherent to GNNs. For productivity, we develop parameterized hardware templates using High-level Synthesis (HLS) and create user-friendly Application Programming Interfaces (APIs). We deploy our accelerator design on both datacenter and embedded FPGAs. Specifically, we test it on Alveo U280, AMD/Xilinx PYNQ-Z1, and ZCU104, which are comparable to state-of-the-art space-grade FPGAs. We evaluate the proposed model on multiple datasets, including MSTAR, SynthWakeSAR, and GBSAR. Compared with the state-of-the-art models, the proposed GNN model achieves higher or comparable accuracy with substantially less computational complexity. Furthermore, compared with CPU and GPU implementations, our FPGA-based accelerators consistently deliver lower latency, improved throughput, and higher energy efficiency.