Fast Software Implementation of a CCSDS LDPC Encoder

The CCSDS LDPC codes are used by NASA and other space agencies in modern transceivers. These codes were designed to be easy to decode by ensuring the parity check matrix is sparse. However, the encoding requires multiplication by a non-sparse generator matrix. The encoder can be efficiently mapped to an FPGA by exploiting the high level of parallelism. All published work on the CCSDS LDPC encoders describes FPGA implementations. With the almost universal acceptance of software defined radio (SDR) in modern ground stations, the LDPC codec must be implemented in software operating on standard CPUs. The authors encountered a counter-intuitive situation where the decoder operates faster than the encoder when implemented in software. This surprising result is mainly due to the availability of highly optimized software decoders, and lack of such optimized encoders. This paper provides an in-depth discussion of mapping the encoder to a modern CPU. The optimized encoder achieves over 100x higher throughput than the fastest open-source version.