A RISC-V Multi-Core Accelerator for Flexible High-Performance In-Network Computing

In this paper, we propose a universal multi-core processor architecture tailored for flexible and high-performance in-network computing scenarios. With the rapid increase in network speed and the emergence of in-network computing applications, the number of packet processing engines in packet processors has surged, leading to a corresponding increase in communication demands between these engines. This, in turn, has posed new challenges to the multi-core design of packet processors. We analyze the differences in inter-core traffic between conventional multi-core processors and packet processors and design a hybrid ring-similar interconnection architecture. This architecture employs a novel node layout and introduces unidirectional channels to eliminate conflicts in the network. Eliminating conflicts reduces per-hop latency and contention latency, while leveraging the ring-similar topology minimizes serialization latency. Additionally, in response to the demands of in-network computing, we have designed a novel packet processing engine. This core extends the relevant instruction set and, by employing blocking multithreading and multiple issue techniques, is capable of supporting both SIMD and MIMD. This significantly improves the IPC when executing in-network computing tasks. The experimental results demonstrate that our design achieves significant improvements in throughput and latency for various in-network computing applications. In terms of area efficiency, it shows improvements ranging from 1.9 to 35.3 times compared to the current state-of-the-art across different applications.