Ferroelectric FET LUT Based Energy Efficient and Secure Logic Locking Resilient to SAT Attacks

Logic locking is used to protect intellectual property (IP) from reverse engineering. Recent techniques for logic locking incorporate numerous key gates into the original circuits, enhancing protection against boolean satisfiability (SAT) attacks. However, this study introduces a novel approach to logic locking by utilizing ferroelectric field effect transistors (FeFETs) to address the area and energy overheads commonly associated with CMOS based logic locking methods. By leveraging the tunable characteristics of FeFETs for the first time, this work demonstrates that adjusting the thickness of the ferroelectric layer <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{t}_{\text{fe}})$</tex> can enable FeFETs act as a switch and exhibit hysteresis for nonvolatile memory applications. FeFET based LUTs are introduced, leveraging the nonvolatile memory properties to securely store confidential key information within locked circuits. At a supply voltage of 0.5V, the FeFET based ISCAS C17 circuit exhibits ~4.2x times lower propagation delay and ~2.6x lower energy consumption compared to CMOS based alternatives.