High Speed Low Power 16×16 Dadda Multiplier by Utilizing Reversible Gates

A high-speed 16×16 Dadda multiplier tailored for FPGA deployment is designed and implemented in this study. The Dadda algorithm, known for its efficient reduction of partial products, offers significant improvements over traditional array multipliers by minimizing computational delay and hardware complexity. Implemented in Verilog using Xilinx Vivado 2018.3, the proposed multiplier is tailored for applications demanding high-speed arithmetic operations, like image processing, machine learning, and digital signal processing. Furthermore, the integration of reversible logic gates enhances computational efficiency by reducing power consumption and resource utilization. Simulation and performance analysis demonstrate that the proposed design undergoes rigorous simulation and synthesis, demonstrating a delay of 4.638ns, reduced power consumption up to 0.474w, and optimal resource utilization compared to conventional multiplier architectures. With its high-performance characteristics and reduced energy footprint, the proposed multiplier presents a promising solution for real-time and embedded computing applications.