Design of a Loop-Unrolled SAR ADC Based on Recycling Comparators

This paper proposes a novel structure of analog-to-digital converter (ADC) based on a Loop-Unrolled analog-to-digital converter SAR ADC. The two-stage SAR ADC architecture utilizes a SAR-sub ADC with comparator-reused Loop-unrolled structure in the first stage to rapidly quantify the most significant bits, and a simple traditional SAR-sub ADC in the second stage. The overall architecture is “6+8”, finely and low-power quantifying the least significant bits. Due to the rapid analog-to-digital conversion in the front stage, the capacitance size in the second-stage capacitor array is reduced, further speeding up the settling time of residues in the second stage, enhancing the quantization speed, and reducing power consumption. At the same time, the binary-weight recombination redundant bits are adopted in the second-stage capacitor array, which can tolerate the impact of partial offset. Based on the SMIC 55 nm CMOS process, with a sampling rate of 100 MS/s, simulation results show that the proposed ADC architecture achieves a Signal to Noise and Distortion Ratio (SNDR) of 72.35 dB, a Spurious Free Dynamic Range (SFDR) of 85.55 dB, power consumption of 2.57 mW, and a Figure of Merit (FOM) of 6.72 fj/conv-step.