High-Speed and Energy Efficient Universal Shift Register Using Novel Hybrid CNTFET-MOSFET D Flip-Flops for Modern VLSI System

This paper presents the Design of a Universal Shift Register making use of a Novel hybrid D flip-flop, which integrates MOSFET, CNTFET and GDI technologies. The proposed hybrid version targets enhancements in power efficiency, switching speed, area optimization and enhanced Noise Gain. Comparative evaluation is carried out in traditional Universal Shift Register designs implemented with purely CNTFET based D flip-flops. The results display that the hybrid Universal Shift Register is more efficient when compared to the purely CNTFET Universal Shift Registers (USR) which utilises higher transistor count which rapidly increases the time delay and also which has a high Noise Margin. This modern approach provides ultimate stability among overall performance and energy consumption and reduced Time Delay with low Noise Gain, making it exceptionally suitable for low-energy VLSI applications. The hybrid USR model offers a 25.64% power efficiency improvement, consuming <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$257.5 \mu ~\mathrm{W}$</tex> compared to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$346.25 \mu ~\mathrm{W}$</tex> for the CNTFET model. It reduces time delay by 86.75%, from 3412.66 ps to 452.02 ps, and lowers power noise gain by 74.73%, enhancing noise performance for low-power VLSI applications.