Comparative Analysis of Power and Delay Efficient Dynamic Logic Techniques Under Process Variations

With the continuous scaling of transistor technology, power consumption and propagation delay have become critical concerns in modern Very Large Scale Integration design. This paper presents a comparative analysis of various power and delay efficient dynamic logic techniques, including conventional Domino logic, foot-driven stack transistor logic (FDSTL), footer voltage controlled dual keeper Domino logic (FVCDKDL), clock delayed dual keeper Domino logic (CDDK), low leakage clock keeper Domino logic (LLCKDL), and LECTOR-based FDSTL. The study evaluates these techniques under different process corners—Typical-Typical (TT), Fast-Fast (FF), Slow-Slow (SS), Fast-Slow (FS), and Slow-Fast (SF)—to assess their robustness against fabrication-induced variations. Simulation results show that while FVCDKDL and LLCKDL reduce power consumption by over 99% compared to Domino logic, techniques such as CDDK and Domino logic exhibit failures under extreme process conditions. FVCDKDL achieves the lowest power consumption, with a reduction exceeding 99.3% in the FF corner, whereas LECTOR FDSTL consumes up to 83% lower power than Domino logic in the FS corner. Delay analysis further highlights that FVCDKDL provides up to 10% lower propagation delay across all corners, while LECTOR FDSTL exhibits severe performance degradation, experiencing a high delay rise. These findings underscore the importance of selecting robust circuit techniques that ensure efficiency across varying fabrication conditions.