Design and Analysis of Phase Frequency Detector with Blind Zone

This work focuses on the implementation and anal-ysis of three Phase Frequency Detectors (PFDs) with reset signal generated by AND gates, which are designed by using three different CMOS design styles, such as static CMOS, pseudo-NMOS, and pass transistor logic. The design process begins with the creation and simulation of schematics, with a strong emphasis on optimizing circuit components, such as logic gates and registers, for efficient performance. The PFDs are designed and simulated using Cadence with GPDK 180 nm technology. Post-layout simulations are conducted to verify the PFD's functionality. The test setup to compare the performance of the three types of PFDs is designed. The blind zone and power consumption of each design are compared. This comprehensive evaluation helps in understanding how different design styles affect the blind zone of the Phase Frequency Detector (PFD). It provides insights for selecting the suitable design based on application requirements.